1. Field of the Invention
The present invention is related to integrated circuit fabrication. More specifically, the present invention is related to a method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model.
2. Related Art
Dramatic improvements in semiconductor integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies.
Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to perfectly control these complex physical and chemical interactions, these processes typically have process variations that can cause the characteristics of the actual integrated circuit to be different from the desired characteristics. If this difference is too large, it can lead to manufacturing problems which can reduce the yield and/or reduce the performance of the integrated circuit.
Consequently, to be economically viable, a semiconductor manufacturing process has to be robust with respect to process variations, i.e., it must be able to tolerate a large enough range of process variations. (We describe the present invention in the context of “depth of focus,” which usually refers to process variations in photolithography. But, it will be apparent to one skilled in the art that the present invention can be readily applied to include other manufacturing process variations, such as, dose variation, resist thickness variations, etch variations, and doping variations.)
Specifically, improving the depth of focus directly results in cost savings. This is because it can substantially increase the throughput by reducing the amount of time spent on inspection, servicing, and maintenance of the equipment. In addition, the actual process conditions encountered during manufacturing may vary due to a variety of reasons. For example, topographical variations on the wafer can occur due to imperfections in the chemical-mechanical polishing process step. As a result, improving the depth of focus can increase the yield for chips that are manufactured in the presence of these process variations.
Unfortunately, improving depth of focus can be very challenging, especially at deep submicron dimensions. To improve the manufacturability of integrated circuits, designers typically use design rule tables that specify what size and shapes of features may be drawn in a design. Unfortunately, at deep submicron dimensions, design rule tables can be extremely large and unwieldy. Moreover, design rule tables can be overly restrictive which can prevent designers from being able to achieve the best device performance.
Hence, what is needed is a method and an apparatus to identify a manufacturing problem area in a mask layout so that it can be corrected, thereby improving the manufacturability of the mask layout.